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| 1 of 22 rev: 061107 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds28cz04 combines 4kbit (512 x 8) eeprom with 4 pio lines. communication with the device is accomplished with an industry standard i2c and smbus? interface. the memory is organized as two segments of 256 bytes with single byte and up to 16- byte block write capability. individual pio lines may be configured as inputs or outputs. the power-on state of pio programmed as outputs is stored in non- volatile memory. all pio may be reconfigured by the user through the serial interface. applications ? 4g sfp copper modules ? sff-8472, sfp fiber modules ? raid systems ? servers typical operating circuit v cc1 v cc2 max3982 pe1 los pe0 outlev in+ out+ in- out- tx_disable losle v gnd ep v cc t los (from receiver) connect to v cc or gnd v cc ds28cz04 sda scl mrz pio3 pio0 pio2 wp pio1 a 2 a 1 gnd mod-def1 mod-def2 v ee t v ee t from sfp connecto r small form-factor pluggable (sfp) circuit features ? 4kbit (512 x 8) eeprom organized in two 256- byte blocks ? single byte and up to 16-byte eeprom write sequences ? write-protect control pin for the entire eeprom array ? endurance 200k cycles per block at 25c; 10ms max eeprom write cycle ? 4 pio lines ? each pio is configured to input or output mode on startup by stored value ? all pios are reconfigurable after startup ? serial interface user-programmable for i2c bus and smbus compatibility ? supports 100khz and 400khz i2c communica- tion speeds ? operating range: 2.0v to 5.25v, -40c to +85c ? 4mm x 4mm 12-pin tqfn package ordering information part temp range pin-package DS28CZ04G-4+ -40 c to +85 c tqfn12-ep * 4x4mm2 DS28CZ04G-4+t -40 c to +85 c tqfn12-ep * 4x4mm2 tape-and-reel *ep = exposed paddle +denotes lead-free package. pin configuration 12 11 10 9 8 7 1 2 3 4 5 6 a 1 a 2 pio3 wp mrz vcc pio2 pio1 pio0 gnd sda scl thin 12-lead 4mm 4mm qfn (top view) package outline drawing 21-0139 package code t1244+4 ds28cz04 4kbit i2c/smbus eeprom with nonvolatile pio www.maxim-ic.com smbus is a trademark of intel corp.
ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 2 of 22 absolute maximum ratings voltage range on any pin relative to ground -0.5v, +6v maximum current sda, scl, a2, a1, wp, mrz pin 20ma maximum current each pio pin 20ma maximum gnd and v cc current 100ma operating temperature range -40c to +85c junction temperature +150c storage temperature range -55c to +125c soldering temperature see ipc/jedec j-std-020 stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rati ng conditions for extended peri ods may affect device. electrical characteristics (-40c to +85c, see note 1) parameter symbol conditions min typ max units supply voltage v cc 2.0 5.25 v standby current (note 2) i ccs bus idle, v cc = 5.25v 1.5 4 a operating current i cca bus active at 400khz, v cc = 5.25v 250 500 a programming current i prog v cc = 5.25v 500 1000 a power-up wait time t poip (note 3) 100 s eeprom programming time t prog 10 ms endurance n cycle at +25c (notes 4, 5) 200k ? data retention t ret at +85c (notes 5, 6) 40 years pio pins, see figures 8, 9 low-level output voltage v ol 1ma sink current 0 0.4 v high-level output voltage v oh 500 a source current v cc - 0.5v v low-level input voltage v il -0.3 0.3 v cc v high-level input voltage v ih 0.7 v cc v cc + 0.3v v output data valid time t pv 1 s pio read setup time t ps (note 5) 150 ns pio read hold time t ph (note 5) 150 ns leakage current i l high impedance, at v ccmax -1 +1 a scl, sda, a2, a1, wp, mrz pins (note 7), see figure 6 low level input voltage v il -0.3 0.3 v cc v high level input voltage v ih (note 8) 0.7 v cc v ccmax + 0.3v v hysteresis of schmitt trigger inputs v hys (notes 5, 9) 0.05 v cc v low level output voltage v ol at 4ma sink current, open drain 0.4 v output fall time from v ihmin to v ilmax (notes 5, 10) t of bus capacitance from 10pf to 400pf 20 + 0.1c b 250 ns pulse width of spikes that are suppressed by the input filter t sp sda and scl pins only (note 5) 50 ns ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 3 of 22 parameter symbol conditions min typ max units input current with an input voltage between 0.1v cc and 0.9v ccmax i i (note 11) -10 10 a input capacitance c i (notes 5, 9) 10 pf scl clock frequency f scl (note 12) 400 khz bus time-out t timeout (note 12) 25 75 ms hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd:sta (note 13) 0.6 s v cc 2.7v 1.3 low period of the scl clock (note 13) t low v cc < 2.7v 1.5 s high period of the scl clock t high (note 13) 0.6 s setup time for a repeated start condition t su:sta (note 13) 0.6 s v cc 2.7v 0.3 0.9 data hold time (notes 14, 15) t hd:dat v cc < 2.7v 0.3 1.1 s data setup time t su:dat (notes 13, 16) 100 ns setup time for stop condition t su:sto (note 13) 0.6 s bus free time between a stop and start condition t buf (note 13) 1.3 s capacitive load for each bus line c b (notes 5, 13) 400 pf note 1: specifications at -40 c are guaranteed by design and characterization only and not production tested. note 2: to the first order, this current is independent of the supply voltage value. note 3: all pio are tri-stated at beginning of reset prior to setting to power-on values. note 4: this specification is valid for each 16-byte memory block. note 5: not production tested. guaranteed by design or characterization. note 6: eeprom writes can become nonfun ctional after the data-retentio n time is exceeded. long-time storage at elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125c or 40 years at +85c. note 7: all values are referenced to v ihmin and v ilmax levels. note 8: the maximum specification value is guaranteed by design, not production tested. note 9: applies to sda and scl. note 10: c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times according to i2c-bus specification v2.1 are allowed. note 11: the ds28cz04 does not obstruct the sda and scl lines if v cc is switched off. note 12: the minimum scl clock frequency is limited by the bus timeout feature. if the cm bit is 1 and scl stays at the same logic level or sda stays low fo r this interval, the ds28cz04 behaves as though it has sensed a stop condition. note 13: system requirement note 14: the ds28cz04 provides a hold time of at leas t 300ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 15: the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 16: a fast-mode i2c-bus device can be used in a st andard-mode i2c-bus system, but the requirement t su:dat 250ns must then be met. this is automatically t he case if the device does not stretch the low period of the scl signal. if such a device does st retch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000 + 250 = 1250ns (according to the standard-mode i2c-bus specification) before the scl line is released. ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 4 of 22 pin description pin name function 1 a1 device address bit 1 2 a2 device address bit 2 3 pio3 pio line #3 4 pio2 pio line #2 5 pio1 pio line #1 6 pio0 pio line #0 7 v cc power supply input 8 mrz master reset (active-low). performs a rese t of the serial interface and the pios without power-cycling the device. 9 wp write protect input, to be connected to v cc or gnd. when connected to v cc , the entire eeprom array is write-protected. normal re ad/write access when connected to gnd. changing the pin state during a write ac cess will cause unpredictable results. 10 scl i2c/smbus serial clock input; must be tied to v cc through a pullup resistor. 11 sda i2c/smbus bidirectional serial data line; must be tied to v cc through a pullup resistor. 12 gnd ground supply for the device. ep gnd exposed paddle. solder evenly to the boar d?s ground plane for proper operation. see application note 3273 for additional information. overview the ds28cz04 consists of a serial i2 c/smbus interface, 4k-bits of eeprom and four bidirecti onal pio channels, as shown in the block diagram in figure 1. the device communicates with a host processor through its i2c interface in standard-mode or in fast-mode; the user c an switch the interface from i2c bus to smbus mode. two address pins allow 4 ds28cz04 to reside on the same bu s segment. a master reset pin permits a full device reset without power cycling. the device has a memory range of 512 bytes, organized as two segments (lower half, upper half) of 256 bytes (figure 2). the memory map and device addressing is compatible with sff-8472 digital diagnostic address assignments. the entire eeprom can be write-protected by tying the wp pin to v cc . the pio pins can be accessed through one address (= single-ad dress mode) or through separate addresses (= multi-address mode). pio direct access addressing allows fast gener ation of data patterns and fast sampling. the ds28cz04 includes several eeprom registers for the us er to select whether the device powers up in sff mode and to define the power-on default conditions for indi vidual pio output state (high, low, in output mode), individual pio data direction (in, out), individual pio output type (push-pull, open drain), individual pio read bit inversion (true, false). once powered up, the pio setti ngs can be overwritten through sram registers without affecting the power-on defaults. ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 5 of 22 figure 1. block diagram serial interface control power distribu- tion v cc gnd scl sda a 2 a 1 4-kbit eeprom pio control pio0 pio1 pio2 pio3 wp mrz figure 2a. memory map (device address = a0h) address type access description 00h to 74h eeprom r/w user memory 75h eeprom r/w special function/user memory; controls whether device powers-up into sff mode 76h eeprom r/w power-on default for pio output state and direction for all pios 77h eeprom r/w power-on default for pio output type and read- inversion for all pios 78h to 79h ? r reserved (reads ffh) 7ah sram r/w direction setting for all pios and device control/status register 7bh sram r/w pio read-inversion and pio output type for all pios 7ch to 7fh sram r/w pio r ead/write access registers 80h to ffh eeprom r/w user memory figure 2b. memory map (device address = a2h) address type access description 00h to 6dh eeprom r/w user memory eeprom r/w sff mode off: user memory 6eh ? r sff mode on: sff optional status register 6fh to efh eeprom r/w user memory f0h to ffh ? r reserved (reads ffh) ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 6 of 22 detailed register descriptions special function/user memory (device address = a0h) addr b7 b6 b5 b4 b3 b2 b1 b0 75h 1 0 1 0 1 0 1 0 there is general read and write access to this address. if programmed to aah, as shown in the bit pattern above, the sff mode bit at memory addres s 7ah (device address = a0h) will be set to 1 after the next power-up , acti- vating sff mode with memory address 6e h (device address a2h) functioning as the sff optional status register. factory-default: 00h power-on default for pio output state and direction (device address = a0h) addr b7 b6 b5 b4 b3 b2 b1 b0 76h pod3 pod2 pod1 pod0 pov3 pov2 pov1 pov0 there is general read and write access to this address. factory-default: f0h bit description bit(s) definition pov0: power-on state pio0 b0 power-on default output state of pio0 pov1: power-on state pio1 b1 power-on default output state of pio1 pov2: power-on state pio2 b2 power-on default output state of pio2 pov3: power-on state pio3 b3 power-on default output state of pio3 pod0: power-on direction pio0 b4 power-on default direction of pio0; 0 ? output, 1 ? input pod1: power-on direction pio1 b5 power-on default direction of pio1; 0 ? output, 1 ? input pod2: power-on direction pio2 b6 power-on default direction of pio2; 0 ? output, 1 ? input pod3: power-on direction pio3 b7 power-on default direction of pio3; 0 ? output, 1 ? input power-on default for pio output type and read inversion (device address = a0h) addr b7 b6 b5 b4 b3 b2 b1 b0 77h pot3 pot2 pot1 pot0 pim3 pim2 pim1 pim0 there is general read and write access to this address. factory-default: f0h ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 7 of 22 bit description bit(s) definition pim0: power-on read inversion pio0 b0 power-on default state of read-inversion bit of pio0; 0 ? no inversion, 1 ? inversion pim1: power-on read inversion pio1 b1 power-on default state of read-inversion bit of pio1; 0 ? no inversion, 1 ? inversion pim2: power-on read inversion pio2 b2 power-on default state of read-inversion bit of pio2; 0 ? no inversion, 1 ? inversion pim3: power-on read inversion pio3 b3 power-on default state of read-inversion bit of pio3; 0 ? no inversion, 1 ? inversion pot0: power-on output type pio0 b4 power-on default output type of pio0; 0 ? push-pull, 1 ? open drain pot1: power-on output type pio1 b5 power-on default output type of pio1; 0 ? push-pull, 1 ? open drain pot2: power-on output type pio2 b6 power-on default output type of pio2; 0 ? push-pull, 1 ? open drain pot3: power-on output type pio3 b7 power-on default output type of pio3; 0 ? push-pull, 1 ? open drain direction and control/status register (device address = a0h) addr b7 b6 b5 b4 b3 b2 b1 b0 7ah admd cm busy sff dir3 dir2 dir1 dir0 there is general read and write access to this address. bit 5 is read-only. the power-on default of bits 0 to 3 is copied from memory address 76h (device addr ess = a0h) bits 4 to 7, respectively. bit description bit(s) definition dir0: direction pio0 b0 direction of pio0; 0 ? output, 1 ? input dir1: direction pio1 b1 direction of pio1; 0 ? output, 1 ? input dir2: direction pio2 b2 direction of pio2; 0 ? output, 1 ? input dir3: direction pio3 b3 direction of pio3; 0 ? output, 1 ? input sff: sff mode bit b4 sff mode control; 0 ? sff mode off, 1 ? sff mode on. see memory map (device address = a2h) and sff optional status register description for details. the sff mode bit, when set to 1, does not change the direction of pio0 and pio1 to input. busy: eeprom busy indicator b5 if this bit reads 1, an eeprom write cycle (a0h or a2h device address) is in progress. (smbus mode only; reads 0 in i2c bus mode) cm: communication mode b6 selects mode for the serial communication interface. 0: i2c bus mode (power-on default) 1: smbus mode admd: pio address mode b7 selects address mode for pio read/ write access. see pio read/write access registers for details. 0: multi-address m ode (power-on default) 1: single-address mode ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 8 of 22 pio read-inversion and output type (device address = a0h) addr b7 b6 b5 b4 b3 b2 b1 b0 7bh ot3 ot2 ot1 ot0 imsk3 imsk2 imsk1 imsk0 there is general read and write access to this address. the power-on default is copied from memory address 77h (device address = a0h). bit description bit(s) definition imsk0: read-inversion control of pio0 b0 0 ? no inversion, 1 ? data read from pio0 is inverted imsk1: read-inversion control of pio1 b1 0 ? no inversion, 1 ? data read from pio1 is inverted imsk2: read-inversion control of pio2 b2 0 ? no inversion, 1 ? data read from pio2 is inverted imsk3: read-inversion control of pio3 b3 0 ? no inversion, 1 ? data read from pio3 is inverted ot0: output type of pio0 b4 0: ? push-pull, 1 ? open drain ot1: output type of pio1 b5 0: ? push-pull, 1 ? open drain ot2: output type of pio2 b6 0: ? push-pull, 1 ? open drain ot3: output type of pio3 b7 0: ? push-pull, 1 ? open drain pio read/write access registers (device address = a0h) addr b7 b6 b5 b4 b3 b2 b1 b0 pio address mode iv3 iv2 iv1 iv0 ov3 ov2 ov1 ov0 single 7ch 1 1 1 iv0 1 1 1 ov0 multi 00h (no function) single 7dh 1 1 1 iv1 1 1 1 ov1 multi 00h (no function) single 7eh 1 1 1 iv2 1 1 1 ov2 multi 00h (no function) single 7fh 1 1 1 iv3 1 1 1 ov3 multi there is general read and write access to these registers. bits shown as 1 have no function; their state cannot be changed. ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 9 of 22 bit description bit(s) definition ov0: output value of pio0 ? logic output state of pio0 if dir0 = 0 (output) ov1: output value of pio1 ? logic output state of pio1 if dir1 = 0 (output) ov2: output value of pio2 ? logic output state of pio2 if dir2 = 0 (output) ov3: output value of pio3 ? logic output state of pio3 if dir3 = 0 (output) iv0: input value of pio0 ? logic state read from pio0 xor?ed with imsk0 iv1: input value of pio1 ? logic state read from pio1 xor?ed with imsk1 iv2: input value of pio2 ? logic state read from pio2 xor?ed with imsk2 iv3: input value of pio3 ? logic state read from pio3 xor?ed with imsk3 figure 3 shows a simplified schematic of a pio. the flip flops are accessed through the pio r/w access registers and memory addresses 7ah and 7bh (devic e address = a0h). they are initia lized at power-up or during reset according to the data stored at memory addresses 76h and 77h (device address = a0 h). when a pio is configured as input, the pio output is tri-stated (high impedance). when a pio is configured as output, the pio input is the same as the output state xor'ed with the corresponding read inversion bit. figure 3. pio simplified schematic d q clk d q clk d q clk d q clk dirn ovn otn vcc d q clk imskn pion pin to serial interface ivn otn from serial interface clk dirn from serial interface ovn from serial interface imskn from serial interface note : otn, dirn, ovn and imskn are nonvolatile based on power-on register values (memory addresses 76h and 77h, device address a0h) ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 10 of 22 sff optional status register (device a ddress = a2h, only if sff mode is on) addr b7 b6 b5 b4 b3 b2 b1 b0 6eh 0 0 0 0 0 txf los 0 this register is read only. the functional assignments of the individual bits are explained in the table below. bits 0 and 3 to 7 have no function; they always read 0 and cannot be set to 1. bit description bit(s) definition los: loss of signal b1 reports the logical state of pio0; in sff-8472 compatible modules, pio0 is connected to the loss of signal indicator txf: tx_fault b2 reports the logical state of pio1; in sff-8472 compatible modules, pio1 is connected to the tx_fault indicator device operation the typical use of the ds28cz04 in an application involves writing to and reading from the memory and accessing the pios. all these activities are controlled through t he i2c/smbus serial interfac e. since the ds28cz04 has memory areas and registers of different characteristics there are several special cases to consider. see section read and write for details. serial communication interface general characteristics the serial interface uses a data line (sda) plus a cloc k signal (scl) for communication. both sda and scl are bidirectional lines, connected to a positive supply voltage through a pullup resistor. when there is no communication, both lines are high. the output stages of devices connected to the bus must have an open-drain or open-collector to perform the wire d-and function. data can be transferred at rates of up to 100kbps in the standard-mode, up to 400kbps in the fast-m ode. the ds28cz04 works in both modes. a device that sends data on the bus is defined as a tran smitter, and a device receiving data as a receiver. the device that controls the communication is called a ?maste r.? the devices that are controlled by the master are ?slaves.? the ds28cz04 is a slave device. slave address/direction byte to be individually accessed, each device must have a slav e address that does not conflict with other devices on the bus. the slave address to which th e ds28cz04 responds is shown in figure 4. the slave address is part of the slave-address/direction byte. the upper 4 bits of the slav e address of the ds28cz04 are set to 1010b. bits a1 and a2 correspond to the a1 and a2 pins; to be selected the device must be addressed with a1 and a2 bits matching the logical state of the respective pins. figure 4. ds28cz 04 slave address a6 a5 a4 a3 a2 a1 a0 1 0 1 0 a2 a1 p0 r/w 7-bit slave address most signi- ficant bit determines read or write see text pin states ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 11 of 22 as a 512 byte memory device, the ds28cz04 needs 9 addr ess bits to access a memory location. the p0 bit transmitted in place of the a0 address bit specifies whethe r the ?lower half? (0b) or the ?upper half? (1b) of the memory is addressed. this causes the ds28cz04 to occ upy two logical slave addresses, one for each half of the memory. throughout this document, the lower half of the memory is referenced as device address a0h and the upper half as device address a2h . the addresses a0h and a2h are correct if the a1 and a2 pins are tied to logic 0. for different conditions at these pins the slave address changes accordingly. the last bit of the slave- address/direction byte (r/ w ) defines the data direction. when set to a 0, subsequent data will flow from master to slave (write access mode); when set to a 1, data will flow from slave to master (read access mode). although the p0 bit is also transmitted when acce ssing the ds28cz04 in read mode, its value is ignored (don?t care); instead, the value transmitted in the most recent write access applies . i2c/smbus protocol data transfers may be initiated only when the bus is not busy. the master generates the serial clock (scl), controls the bus access, generates the start and st op conditions, and determines the number of bytes transferred on the data line (sda) between start and stop. data is transferred in bytes with the most significant bit being transmitted first. after each byte follows an ac knowledge bit to allow synchronization between master and slave. during any data transfer, sda must remain stabl e whenever the clock line is high. changes in sda line while scl is high will be interpreted as a start or a stop . the protocol is illustrate d in figure 5. for detailed timing references see figure 6. figure 5. i2c/smbus pr otocol overview scl sda 12 678 a ck 9 9 12 8 ms-bit r/ w slave address ack bit acknowledgment from receiver ack bit start condition ack repeated if more bytes are transferred stop condition repeated start condition idle bus idle or not busy both, sda and scl, are inactive, i. e., in their logic high states. start condition to initiate communication with a slave, the master has to generate a start condition. a start condition is defined as a change in state of sda from high to low while scl remains high. stop condition to end communication with a slave, the master has to gener ate a stop condition. a stop condition is defined as a change in state of sda from low to high while scl remains high. repeated start condition repeated starts are commonly used for read accesses after having specified a memory address to read from in a preceding write access. the master can use a repeated start condition at the end of a data transfer to immediately initiate a new data transfer following the current one. a repeated start condition is generated the same way as a normal start condition, but without leaving the bus idle after a stop condition. ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 12 of 22 data valid with the exception of the start and stop condition, tr ansitions of sda may occur only during the low state of scl. the data on sda must remain valid and unchanged du ring the entire high pulse of scl plus the required setup and hold time (t hd:dat after the falling edge of scl and t su:dat before the rising edge of scl, see figure 6). there is one clock pulse per bit of data. data is shift ed into the receiving device dur ing the rising edge of the scl pulse. when finished with writing, the master must release t he sda line for a sufficient amount of setup time (minimum t su:dat + t r in figure 6) before the next rising edge of scl to start reading. the slave shifts out each data bit on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. the master generates all scl clock pulses, including those needed to read from a slave. acknowledged by slave usually, a slave device, when addressed, is obliged to gene rate an acknowledge after the receipt of each byte. the master must generate a clock pulse that is associated wi th this acknowledge bit. a device that acknowledges must pull sda low during the acknowledge clock pulse in such a way that sda is stable low during the high period of the acknowledge-related clock pulse plus the required setup and hold time (t hd:dat after the falling edge of scl and t su:dat before the rising edge of scl). acknowledged by master to continue reading from a slave, the master is obliged to generate an acknow ledge after the receipt of each byte. the master must generate the clock pulse for each ackn owledge bit and, during the acknowledge clock pulse, pull sda low in such a way that sda is stable low during the high period of the ackn owledge-related clock pulse. the setup and hold time (t hd:dat after the falling edge of scl and t su:dat before the rising edge of scl) also apply to the master. not acknowledged by slave a slave device may be unable to receive or transmit da ta, e.g., because it is busy. in smbus mode, the ds28cz04 will always acknowledge its slave addres s. however, some time later the devic e may refuse to accept data, e.g., because of an invalid access mode or an eeprom write cycle in progress. in this case the ds28cz04 will not acknowledge any of the bytes that it refuses and will leave sda high du ring the high period of the acknowledge- related clock pulse. see section read and write for a detailed list of situations where the ds28cz04 does not acknowledge. not acknowledged by master at some time when receiving data, the master must signal an end of data to the slave device. to achieve this, the master does not acknowledge the last byte that it has re ceived from the slave. in response, the slave releases sda, allowing the master to generate the stop condition. figure 6. i2c/smbus timing diagram scl sda stop start t buf t hd:sta t low t r t hd:dat t high t su:dat repeated start t su:sta t f t hd:sta t sp t su:sto spike suppression note: timing is referenced to v ilmax and v ihmin . ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 13 of 22 read and write from the master?s point of view, the ds28cz04 behaves like an memory device with an address range of 512 bytes. as indicated in the memory map, figure 2, t he ds28cz04 has different types of memory: sram, eeprom and read-only areas. the write behavior depe nds on the memory type and the charac teristics of the location that is addressed. the sram re gisters can be written from 1 byte to mu ltiple bytes at a time. the eeprom can be written from 1 byte to 16 or 8 bytes at a time, depending on the memory location. to write to the ds28cz04, the master must address the dev ice in write access mode, i. e., the slave address must be sent with the direction bit set to 0. the slave addres s also determines which of t he memory halves is accessed. the next byte sent in write access mode is the address of the memory location to be written to (?write pointer?) or to start reading from (?read pointer?) if the write access is terminated without sending dat a (?dummy write?). additional bytes are taken as data for the addressed memory location. to read from the ds28cz04, the master must address the device in read access mode, i.e., the slave address must be sent with the direction bit set to 1. the read poi nter determines the location from which the master starts reading. to set the pointer, the ds28cz04 must be addres sed in write access mode, as described above. write access due to the different memory types, special function regist ers, pio access registers a nd address modes, there are several cases to be distinguished: ? normal eeprom eeprom block of 16 bytes ? short eeprom eeprom block of 8 bytes ? special eeprom eeprom block of 16 bytes with on e or more non-writeable bytes ? reserved block of 16 non-writeable bytes ? sram write sram bytes including pio read/write access registers ? pio direct pio read/write access registers only table 1a maps the various cases to the applicable memory addresses and explains the device behavior in detail. all eeprom writes depend on the state of wp pin. only when the eeprom is not write-protected (wp pin state = 0) is data accepted and transferred to the eeprom. when writing to pio read/ write registers, either by running into their address range or by addressing them direct ly, one needs to further distinguish between pio multi- address mode and pio single address mode. the addres s mode is selected through the admd bit of the direction and control/status register (device address a0h) at address 7ah. in multi-address mode, each pio occupies one memory address whereas in single-address mode all pi os share a single address. see the pio read/write access registers description for details. the pio addres s mode does not affect the device behavior when writing to the eeprom sections. writing to eeprom locations if the ds28cz04 is addressed in write access mode, any dat a bytes that follow the address are written to a 16-byte buffer, beginning at an offset that is determined by the 4 l east significant bits of the target address. this buffer is initialized (pre-loaded) with data from the addressed 16-byte eeprom block. incoming data replaces pre-loaded data. with every byte received, the buf fer's write pointer as well as the read pointer is incremented. if the buffer's write pointer has reached its maximum value of 1111b (normal eeprom and special eeprom) or 0111b (short eeprom) and additional data is received, the pointer wraps around (rolls over ) and the incoming data is written to the beginning of the eeprom write buffer and continuing. the same wrap-around applies to the 4 least-significant bits of the read pointer. this way the read pointer main tains the last address accessed during a write operation, incremented by one. the transfer fr om the buffer to the eeprom begins when the master generates a stop condition. until the write cycle is completed, the ds28cz04 is busy for the duration of t prog . ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 14 of 22 table 1a. write access writing while device is not busy pio mode starting address smbus or i2c bus mode device address = a0h, any 16-byte block except 70h to 7fh ; device address = a2h, any 16-byte block except 60h to 6fh, f0h to ffh (normal eeprom) if wp pin is tied to gnd : slave address is acknowledged; memory address is acknowledged, data is acknowledged; write pointer increments and wraps around from end of block to beginning of block, read pointer = write pointer +1. if wp pin is tied to v cc : data is not acknowledged, no eeprom write cycle takes place; everything else remains the same. device address = a0h, memory address from 70h to 77h (short eeprom) same as ?normal eeprom? except that write pointer wraps around from 77h to 70h . device address = a2h, memory address from 60h to 6fh (special eeprom) sff mode off : same as ?normal eeprom?. sff mode on : data for address 6eh is not acknowledged; everything else is the same as with ?normal eeprom?. device address = a2h, memory address from f0h to ffh (reserved) same as ?normal eeprom? except that data is not acknowledged. device address = a0h, memory address from 78h to 7bh (sram write) slave address is acknowledged; memory address is acknowl- edged, data for address 78h and 79h is not acknowledged; write pointer increments and wraps around from 7fh to 7ah , read pointer = write pointer +1. multi- address device address = a0h, memory address from 7ch to 7fh (pio direct) slave address is acknowledged; memory address is acknowledged, data is acknowledged; write pointer increments and wraps around from 7fh to 7ch , read pointer = write pointer +1. device address = a0h , memory address from 78h to 7fh excluding 7ch (sram write) slave address is acknowledged; memory address is acknowledged, data for addresses 7dh to 7fh and 78h to 79h is not acknowledged; write pointer increments and wraps around from 7fh to 7ah , read pointer = write pointer +1. device address = a0h , memory address = 7ch (pio direct) slave address is acknowledged; memory address is acknowledged, data is acknowledged; write pointer stays at 7ch ; read pointer stays at 7ch . single- address all other cases same as in pio multi-address mode. busy polling while busy, the behavior of the ds 28cz04 depends on the communication mode, which is selected through the cm bit of the direction and control/status register (device address a0h) at address 7ah. tables 1b and 2b show details. the pio address mode does not a ffect the device behavior when busy. in i2c bus mode , when busy the ds28cz04 does not acknowled ge its slave address until the write cycle is completed. the master can access the device by tran smitting the slave address/direction byte and testing whether the address is acknowledged. as soon as the ds 28cz04 acknowledges, the ma ster knows that the device is ready for further activities. in smbus mode , the ds28cz04 always acknowledges its slave address. the only way for the master to detect the completion of the write cycle is through the busy bit in the direction and control/status register (device address a0h) at. to get to this bit the master must first address the ds28cz04 in write access mode, device address a0h, and set the memory address to 7ah (see table 1b). now the master can address the ds28cz04 in read access ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 15 of 22 mode and generate pulses on scl to read data, one byte a fter another without issuing a stop (see table 2b). eventually the busy bit changes from 1 to 0 indicating the end of the write cycle. the busy bit is sampled during the transmission of the byte bef ore it is read out; consequently, the state read out reflects the state at sample time and not the actual state. to get the actual state of the busy bit the master can a) read at the maximum data rate, b) read two bytes in sequence without delay in betwe en and use the busy bit in the second byte or c) in a loop: read one byte, issue a stop, wait, reposition the read pointer, address the ds28cz04 in read mode to get another status byte. table 1b. prepare for busy polling writing while device is busy pio mode starting address smbus mode i2c bus mode device address = a0h, memory address = 7ah slave address is acknowledged; memory address is acknowl- edged; data is not acknowledged; write pointer keeps its last posi- tion; read pointer = 7ah . device address = a0h, any memory address except 7ah either address mode device address = a2h, any memory address slave address is acknowledged; memory address is not acknowl- edged; data is not acknowledged; write pointer keeps its last posi- tion; read pointer = write pointer +1. slave address is not ac- knowledged; memory ad- dress is not acknowledged; data is not acknowledged; write pointer keeps its last position; read pointer = write pointer +1. table 2b. busy polling reading while device is busy pio mode read pointer smbus mode i2c bus mode device address = a0h , memory address = 7ah slave address is acknowledged; data is delivered; read pointer stays at 7ah . device address = a0h , excluding memory address 7ah either address mode device address = a2h , any memory address slave address is acknowledged; no data is delivered; read pointer = last write pointer +1. slave address is not acknowledged; no data is delivered; read pointer stays as is. writing to sram and pio locations if the ds28cz04 is addressed in write access mode, any data bytes that follow the address are directly written to their respective memory location. the pio address mode controls the device behavior when writing to the pio read/write access registers. depending on whether one runs into the pio address range (sram write) or whether one starts at a pio address (pio direct) the pointer a nd data acknowledge behavior is different. table 1a shows the details. the pio address mode is anot her parameter that affects the point er behavior. figure 7 illustrates the possible cases and the sequence in which the addresses are accessed. the common characteristic in both sram write cases is a starting address in the sram block (address range 78h to 7fh) excluding any address used for pio access . data for writeable registers (7ah, 7bh and valid addresses for pio read/write access) is acknowled ged; the write pointer increments and afte r address 7fh rolls over to 7ah. the common characteristic in both pi o direct cases is a starting address within the address range used for pio access . in pio multi-address mode, there are four such addresses (7ch to 7fh); each pio occupies its own address. data is always acknowledged; the write pointer increments to the next pio and eventually wraps around to 7ch. in pio single-address mode, there is exactly one ad dress (7ch) that is shared by all pios. data is always acknowledged; the write pointer stays at 7ch. ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 16 of 22 figure 7. sram and pio writing memory location pio multi-address mode pio single-address mode address function sram write pio di rect sram write pio direct 00h to 77h memory 78h reserved 79h reserved 7ah register 7bh register 7ch pio r/w 7dh pio r/w 7eh pio r/w 7fh pio r/w lower half 80h to ffh memory upper half 00h to ffh memory when writing to a pio, as shown in figure 8, any state change is triggered by the scl pulse that the master generates for the acknowledge bit of byte written to the pi o read/write access register. after the output transition time t pv is expired, the state change is completed. in pio single-address mode all pios change their state approximately at the same time; in this mode the fastest rate for a pio to change its state is f scl /9. in pio multi- address mode each pio is accessed individually; in this m ode when writing in an endless loop the fastest rate for a pio to change its state is f scl /36. transfer of data can be stopped at any moment by a stop condition. when this occurs, data present at the last acknowledged phase is valid. figure 8. pio write access timing sram write sd a scl pio msb data1 lsb a msb data2 lsb a msb data3 lsb a msb (7bh) data lsb a data1 data2 t pv pio direct s a6 a5 a4 a3 a2 a1 p0 0 a msb pio address lsb a msb data1 lsb a msb data2 lsb a sd a scl pio t pv data1 reading memory and pios if the ds28cz04 is addressed in read access mode, the re ad pointer determines the location from which the master will start reading. the read pointer is set when t he ds28cz04 is accessed in write access mode, either for ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 17 of 22 writing data or through a dummy write. at power-on the read pointer is reset to address 00h of the lower half of the memory. a description on how the read pointer is affe cted during write accesses is included in table 1a. in contrast to write accesses where the memory is updated in small blocks of 8 or 16 bytes, all 512 bytes are readable in a single read access. only two cases need to be dist inguished: normal read and pio direct. table 2a explains the cases in detail. table 2a. read access reading while device is not busy pio mode read pointer smbus or i2c bus mode anywhere excluding device address = a0h , memory address from 7ch to 7fh (normal read) slave address is acknowledged; data is delivered; read pointer increments, eventually crossing from lower half to upper half of the memory, and wraps around from upper half ffh to lower half 00h . multi- address device address = a0h , memory address from 7ch to 7fh (pio direct) slave address is acknowledged; data is delivered; read pointer increments and wraps around from 7fh to 7ch, staying in the lower half of memory . anywhere excluding device address = a0h , memory address = 7ch (normal read) slave address is acknowledged; data is delivered; read pointer increments, eventually crossing from lower half to upper half of the memory, and wraps around from upper half ffh to lower half 00h . single- address device address = a0h , memory address = 7ch (pio direct) slave address is acknowledged; data is delivered; read pointer stays at 7ch . the pio address mode in conjunction with the initial read pointer position determines the sequence in which the addresses are accessed. figure 9 illustrates the possible cases. figure 9. memory and pio reading memory location pio multi-address mode pio single-address mode address function normal read pio di rect normal read pio direct 00h to 77h memory 78h reserved 79h reserved 7ah register 7bh register 7ch pio r/w 7dh pio r/w 7eh pio r/w 7fh pio r/w lower half 80h to ffh memory upper half 00h to ffh memory ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 18 of 22 the common characteristic in both normal read cases is a starting address anywhere in the memory excluding any address used for pio access . the read pointer increments after every byte read. this way a series of read accesses reveals memory data of cons ecutive addresses, without any duplic ations or gaps. when reading from reserved areas the master receives ff h bytes. when the end of the upper half of the memory is reached (device address a2h, address ffh) the read pointer wraps around to the start of the lower half of the memory (device address a0h, address 00h). when the end of the lower half of the memory is re ached, the read pointer continues at the start of the upper half of the memory. to change the re ad address, the master has to address the ds28cz04 in write access mode and specify a new memory address. the common characteristic in both pi o direct cases is a starting address within the address range used for pio access . in pio multi-address mode, there are four such addresses (7ch to 7fh); each pio occupies its own address. after a byte is sent to t he master, the read pointer increments to the next pio and eventually wraps around to 7ch. in pio single-address mode, there is exactly one address (7ch) that is shared by all pios. consequently, the master can continue readi ng, but the read pointer stays at 7ch. when reading from a pio, as shown in figure 10, th e sampling takes place on the falling scl edge of the 2 nd -last bit before the acknowledge bit. with pio direct mode, the firs t sample is taken 3 scl cycles earlier, i. e., during the transmission of the a3 bit of the slave address. to be correctly assessed, the pio st ate must not changed during the t ps and t ph interval. in pio single-address mode all pios are sampled simultaneously; in this mode with pio direct access the fastest sample rate for a pio is f scl /9. in pio multi-address mode each pio is sampled individu- ally; in this mode with pio direct access the fastest sample rate for a pio is f scl /36. transfer of data can be stopped at any moment by a stop condition. when this occurs, data from the last sampling instance is lost. figure 10. pio read access timing normal read msb data2 lsb a msb data3 lsb a msb data4 lsb a t ps t ph sampling sampling sampling pio scl sd a msb (7bh) data lsb a data1 data2 data4 data3 data5 pio direct s a6 a5 a4 a3 a2 a1 p0 1 a msb data1 lsb a msb data3 lsb a msb data4 lsb a t ps t ph sampling sampling sampling pio scl sd a data1 data2 data4 data3 data5 with revision a1 devices, the sampling always takes pl ace on the falling scl edge of the last bit before the acknowledge bit. the sampled data, however, is reported to the master one byte late, as shown in figure 10a. the first sample of pio data that the master receives in pio di rect access should be discarded since its timing relative to the transmission of the slave address is undefined. any application firmware developed for revision a1 devices is fully compatible to newer devices. ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 19 of 22 figure 10a. pio read access timing, a1 devices normal read, a1 parts msb data1 lsb a msb data2 lsb a msb data3 lsb a data1 data2 data4 data3 data5 t ps t ph sampling sampling sampling note: data1 was sampled during the transmission of data from address 7ah, or, if reading started at memory address 7bh, during the transmission of the slave address. pio scl sd a msb (7bh) data lsb a pio direct, a1 parts s a6 a5 a4 a3 a2 a1 p0 1 a msb data1 lsb a msb data2 lsb a msb data3 lsb a t ps t ph sampling sampling sampling note: data1 was sampled during the transmission of the slave address of a preceding read or write access. pio scl sd a data1 data2 data4 data3 data5 i2c/smbus communication?legend symbol description symbol description s start condition xx0xx1xxb byte that defines specific bits only adl,0 select for write access to lower half p stop condition adh,0 select for write access to upper half a\ not acknowledged adx,1 select for read access ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 20 of 22 set smbus mode, write 3 bytes starting at address 25h, upper half of the memory, test for end of cycle s adl,0 a 7ah a x1xxxxxxb a p s adh,0 a 25h a ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 21 of 22 s adl,0 a 7dh a p s adx,1 a ds28cz04: 4kbit i2c/smbus eeprom with nonvolatile pio 22 of 22 for i2c systems, the rise time and fall time are meas ured from 30% to 70% of the pullup voltage. the maximum bus capacitance c b is 400pf. the maximum rise time must not ex ceed 300ns. assuming maximum rise time, the maximum resistor value at any given capacitance c b is calculated as: r pmax = 300ns/(c b * ln(7/3)) . for a bus capacitance of 400pf the maximum pullup resistor would be 885 . since an 885 pullup resistor, as would be required to meet the rise time specification and 400pf bus capacitance, is lower than r pmin at 5.25v, a different approach is necessary. the "max. load?" line in figure 12 is generated by first calculating the minimum pullup resistor at any given operating voltage ("minimum r p " line) and then calculating the respective bus capacitance that yields a rise time of 300ns. only for pullup voltages of 4v and lower can the maximum permissible bus capacitance of 400pf be maintained. a reduced bus capacitance of 300pf is acceptable for the entire operating voltage rang e. the corresponding pullup resistor value at the voltage is indicated by the "minimum r p " line. figure 12. i2c fast speed pull up resistor selection chart 0 200 400 600 800 1000 1200 22.533.544.55 pull-up voltage minimum rp (ohms) 0 100 200 300 400 500 600 load (pf) "minimum rp" max. load at min. rp fast mode package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo .) |
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